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Bit
27:26
Name
TXDELAY
Reset
0x0
Access
RW
Description
TX Delay Transmission
Configurable delay before new transfers. Frames sent back-to-back are not delayed.
Value
0
1
2
3
Mode
NONE
SINGLE
DOUBLE
TRIPLE
Description
Frames are transmitted immediately
Transmission of new frames are delayed by a single baud period
Transmission of new frames are delayed by two baud periods
Transmission of new frames are delayed by three baud periods
25
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
24
ERRSTX
0
RW
Disable TX On Error
When set, the transmitter is disabled on framing and parity errors (asynchronous mode only) in the receiver.
Value
0
1
Description
Received framing and parity errors have no effect on transmitter
Received framing and parity errors disable the transmitter
23
ERRSRX
0
RW
Disable RX On Error
When set, the receiver is disabled on framing and parity errors (asynchronous mode only).
Value
0
1
Description
Framing and parity errors have no effect on receiver
Framing and parity errors disable the receiver
22
ERRSDMA
0
RW
Halt DMA On Error
When set, DMA requests will be cleared on framing and parity errors (asynchronous mode only).
Value
0
1
Description
Framing and parity errors have no effect on DMA requests from the USART
DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set
21
BIT8DV
0
RW
Bit 8 Default Value
The default value of the 9th bit. If 9-bit frames are used, and an 8-bit write operation is done, leaving the 9th bit unspecified, the
9th bit is set to the value of BIT8DV.
20
SKIPPERRF
0
RW
Skip Parity Error Frames
When set, the receiver discards frames with parity errors (asynchronous mode only). The PERR interrupt flag is still set.
19
SCRETRANS
0
RW
SmartCard Retransmit
When in SmartCard mode, a NACK'ed frame will be kept in the shift register and retransmitted if the transmitter is still enabled.
18
SCMODE
0
RW
SmartCard Mode
Use this bit to enable or disable SmartCard mode.
17
AUTOTRI
0
RW
Automatic TX Tristate
When enabled, TXTRI is set by hardware whenever the transmitter is idle, and TXTRI is cleared by hardware when transmission starts.
Value
0
1
Description
The output on U(S)n_TX when the transmitter is idle is defined by TXINV
U(S)n_TX is tristated whenever the transmitter is idle
16
AUTOCS
0
RW
Automatic Chip Select
When enabled, the output on USn_CS will be activated one baud-period before transmission starts, and deactivated when
transmission ends.
15
CSINV
0
RW
Chip Select Invert
Default value is active low. This affects both the selection of external slaves, as well as the selection of the microcontroller as a slave.
Value
0
1
Description
Chip select is active low
Chip select is active high
14
TXINV
0
RW
Transmitter output Invert
The output from the USART transmitter can optionally be inverted by setting this bit.
2011-04-12 - d0001_Rev1.10
200
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